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SRAM Memory Design | Samsung | Bangalore

Company: 

Samsung

Location:

Bangalore

Job Type:

Salary:

Full Time

NA

Who can Apply:

Experienced

Experience:

4+ Years

Job Description:

Samsung Semiconductor India Research (SSIR) is hiring an SRAM Memory Design Engineer in Bangalore with 4–10 years of experience in memory design and semiconductor engineering. The role involves designing highly competitive SRAM circuits to meet customer requirements for performance, power, and PPA. The engineer will contribute to the complete development cycle from SPEC to GDS and DK delivery, analyze circuit robustness, review layouts, and identify opportunities to improve design competitiveness. Strong knowledge of SRAM bit cells, read current, standby current, data retention, SNM, RC networks, FINFET fundamentals, semiconductor physics, process variability, parasitics, and layout effects is required. Experience in custom SRAM, compiler SRAM, or ROM development is preferred. This opportunity is suitable for professionals specializing in SRAM memory design, custom memory circuits, semiconductor circuit design, memory IP, VLSI, PPA optimization, and advanced FinFET technologies.

About Company:

Samsung Semiconductor India Research (SSIR) is a major Samsung R&D organization in Bangalore focused on advanced semiconductor technologies, System LSI, Memory, Foundry, and semiconductor IP development. SSIR contributes to technologies including mobile SoCs, AI/ML, 5G/6G, neural processors, storage solutions, serial interfaces, multimedia IPs, and Foundation IP Design. The organization provides engineers with opportunities to work on advanced semiconductor products, memory technologies, circuit design, verification, and global R&D projects. Samsung's semiconductor research environment brings together expertise in VLSI, memory design, analog and digital circuits, SoC development, semiconductor physics, process technologies, and advanced IP development. The SRAM Memory Design Engineer role provides an opportunity to work on SRAM IP development, custom memory circuits, PPA optimization, circuit robustness, FinFET technology, semiconductor physics, layout analysis, and memory design methodologies while collaborating with engineering teams on advanced semiconductor solutions.

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