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Job Description:
Arm is hiring a Senior CPU Verification Engineer in Bangalore, Karnataka, India to develop and support sophisticated CPU Random Instruction Sequences (RIS) tools used for stress verification of next-generation CPU cores. The role focuses on CPU design verification, microarchitecture, test generation, hardware/software interaction, and verification tool development. Candidates should have 5–10 years of proven experience and a B.Tech/B.S. or M.Tech/M.S. degree in Computer Engineering, Electronics Engineering, or Computer Science. Strong skills in C/C++ programming, assembly language, CPU architecture, microarchitecture, and test-case development are essential. Knowledge of RISC-V, x86, MIPS, or Arm architecture, along with familiarity with EDA tools and hardware design verification, is highly desirable. The engineer will work with CPU teams across Arm’s global design centers and contribute to improving stimulus generation, CPU stress testing, verification coverage, and product-quality CPU IP.
About Company:
Arm is a global technology company and a recognized leader in CPU and System IP technology. Arm develops processor architectures and technology that power a wide range of digital products and computing platforms, including smart devices, networking systems, automotive technology, security solutions, storage devices, AI infrastructure, and high-performance computing systems. Arm works with a global ecosystem of technology partners to deliver low-power, high-performance processor technology. Because CPU and System IP require high reliability and a right-first-time design and verification approach, Arm places significant importance on sophisticated design verification, CPU architecture, microarchitecture, stress testing, and verification automation. Engineers joining Arm’s verification teams have opportunities to work on next-generation CPU cores, Random Instruction Sequences, verification tools, processor architecture, hardware/software interaction, and advanced EDA-based verification technologies.
