ASIC Engineering Technical Leader | Design Verification | Verilog, System Verilog, UVM, Testbench

ASIC Engineering Technical Leader responsible for leading end-to-end design verification of high-performance ASICs using Verilog/SystemVerilog, UVM, and testbench methodologies. The role covers verification architecture, simulation, emulation, coverage, silicon bring-up, technical leadership, and mentoring of engineering teams.

About Company:

Cisco Systems is an American multinational technology corporation that develops and sells networking hardware, software, telecommunications equipment, and high-technology services.