ASIC Design Verification Engineer | UVM

ASIC Design Verification Engineer responsible for architecting and developing UVM/SystemVerilog verification environments for complex ASIC blocks, clusters, and top-level designs. The role covers test planning, functional and code coverage, gate-level simulation, emulation, debugging, and ASIC bring-up.

About Company:

Cisco Systems is an American multinational technology corporation that develops and sells networking hardware, software, telecommunications equipment, and high-technology services.